The present invention in general relates to a differential output circuit. More specifically this invention relates to a differential output circuit such as LVDS (Low Voltage Differential Signaling, hereinafter shown as LVDS) having high speed, low voltage and low noise transmission.
FIG. 7 shows a conventional differential output circuit. This differential output circuit is provided with a resistance R1xe2x80x2 whose one terminal is connected to GND, and N-channel MOS transistors M3xe2x80x2 and M4xe2x80x2 whose sources are connected to the other terminal of the resistance R1xe2x80x2.
Further, an inverter circuit 5xe2x80x2, an N-channel MOS transistor M1xe2x80x2 and an N-channel MOS transistor M2xe2x80x2 are provided. The inverter circuit 5xe2x80x2 inverts data VI input through a data input terminal. A gate of the N-channel MOS transistor M1xe2x80x2 is connected to an output terminal of the inverter circuit 5xe2x80x2, and its source is connected to a drain of the N-channel MOS transistor M4xe2x80x2. Agate of the N-channel MOS transistor M2xe2x80x2 is connected to the data input terminal, and its source is connected to a drain of the N-channel MOS transistor M3xe2x80x2.
Further, a gate of the N-channel MOS transistor M3xe2x80x2 is also connected to the output terminal of the inverter circuit 5xe2x80x2, and a gate of the N-channel MOS transistor M4xe2x80x2 is also connected to the data input terminal.
Moreover, the drain of the N-channel MOS transistor M3xe2x80x2 is connected to an output terminal VO+, and the drain of the N-channel MOS transistor M4xe2x80x2 is connected to the output terminal VOxe2x88x92.
In addition, drains of the N-channel MOS transistors M1xe2x80x2 and M2xe2x80x2 are connected to a power-supply potential Vcc.
Further, an external load resistance RT is connected between the output terminals VO+ and VOxe2x88x92.
In this conventional differential output circuit, a constant-current source I1xe2x80x2 turns ON a pair of transistors composed of the N-channel MOS transistors M1xe2x80x2 and M3xe2x80x2 or the N-channel MOS transistors M2xe2x80x2 and M4xe2x80x2 so that a constant current always drives the external load resistance RT.
FIG. 8 is an output waveform chart of the conventional LVDS. Offset level VOS (hereinafter, referred to as VOS) of an output amplitude is determined by the product of the constant-current source I1xe2x80x2 and the resistance R1xe2x80x2. However, in a semiconductor using the conventional differential output circuit, there arises a problem that it is difficulty to control VOS with high accuracy due to the presence of variation in the constant-current source I1xe2x80x2 or the resistance R1xe2x80x2.
The differential output circuit of the present invention which utilizes LVDS for high speed, low-voltage and low noise transmission is provided with the reference voltage circuit which outputs a constant voltage even if temperature, power-supply voltage and manufacturing process vary.
Further, a constant-current circuit section is provided. This constant-current circuit section having a) a reference voltage circuit which outputs a constant voltage even if any of the temperature, power-supply voltage and semiconductor manufacturing process varies, b) a first resistance whose one terminal is connected to GND, c) a first conductive MOS transistor whose source is connected to the other terminal of the first resistance, d) a second conductive MOS transistor whose a source is connected to a power-supply potential and a drain is connected to a drain of the first conductive MOS transistor, and e) an amplification circuit whose an output terminal of the reference voltage circuit is connected to a positive input terminal, a negative input terminal is connected to the source of the first conductive MOS transistor, and an output terminal is connected to a gate of the first conductive MOS transistor.
Further, a mirror circuit section is provided. This mirror circuit section having a) a third conductive MOS transistor whose source is connected to the power-supply potential and gate is connected to a gate of the second conductive MOS transistor, and b) a fourth conductive MOS transistor and a fifth conductive MOS transistor whose sources are connected to a drain of the third conductive MOS transistor.
Further, a data input terminal, a negative output terminal, and a positive input terminal are provided.
Further, a data transmission switch circuit section is provided. This data transmission switch circuit section having a) an inverter circuit which inverts data input through the data input terminal, b) a sixth conductive MOS transistor whose gate is connected to an output terminal of the inverter circuit and drain is connected to a drain of the fourth conductive MOS transistor, c) a seventh conductive MOS transistor whose gate is connected to the data input terminal and drain is connected to a drain of the fifth conductive MOS transistor
Further, gate of the fourth conductive MOS transistor being connected to the data input terminal, gate of the fifth conductive MOS transistor being connected to the output terminal of the inverter circuit, drain of the fourth conductive MOS transistor being connected to the negative output terminal, and drain of the fifth conductive MOS transistor being connected to the positive input terminal.
Further, an offset level adjusting circuit section is provided. This offset level adjusting circuit section having a second resistance whose one terminal is connected to GND and the other terminal is connected to sources of the sixth and seventh conductive MOS transistors.
Further, in the differential output circuit, the reference voltage circuit comprises a noise reduction circuit, a first current driving circuit section, a second current driving circuit section, and an amplification circuit.
The noise reduction circuit is having a) a third resistance, b) a first parasitic capacitance connected between the third resistance and GND, c) a fourth resistance, d) a second parasitic capacitance connected between the fourth resistance and GND.
The first current driving circuit section is having a) a fifth resistance and a sixth resistance connected in series, and b) a first bipolar transistor connected in series with the sixth resistance.
The second current driving circuit section is having a) a seventh resistance, and b) a second bipolar transistor connected in series with the seventh resistance.
In the amplification circuit, a) output terminal is connected to one terminals of the fifth and seventh resistances, b) negative input terminal is connected to a node between the third resistance and the first parasitic capacitor, and c) positive input terminal is connected to anode between the fourth resistance and the second parasitic capacitor.
The other terminal of the third resistance being connected to a node between the fifth and sixth resistances, and the other terminal of the fourth resistance being connected to a node between the seventh resistance and the second bipolar transistor.
Further, in the differential output circuit, the reference voltage circuit is provided with a reference voltage circuit section which is composed of an eight resistance whose one terminal is connected to GND and a ninth resistance whose one terminal is serially connected to the other terminal of the eighth, resistance and the other terminal is connected to a power-supply potential.
Further, in the differential output circuit, in the mirror circuit section, a ratio of transistor sizes of the fourth conductive MOS transistor and the fifth conductive MOS transistor is 1:1/n where n is a positive integer.
Further, the differential output circuit, which uses LVDS in order to obtain high-speed, low-voltage and low-noise transmission, is provided with the reference voltage circuit which outputs a constant voltage even if temperature, power-supply voltage and semiconductor manufacturing process vary.
Further, a constant-current circuit section is provided. This constant-current circuit section is having a) a reference voltage circuit which outputs a constant voltage even if any of the temperature, power-supply voltage and semiconductor manufacturing process varies, b) a first conductive MOS transistor whose source is connected to GND, c) a second conductive MOS transistor whose source is connected to a drain of the first conductive MOS transistor, d) a third conductive MOS transistor whose source is connected to a power-supply potential and a drain and a gate are connected to a drain of the second conductive MOS transistor, and e) an amplification circuit to a positive input terminal which the output terminal of the reference voltage circuit is connected, a negative input terminal is connected to a node between the source of the second conductive MOS transistor and the drain of the first conductive MOS transistor, and an output terminal is connected to a gate of the second conductive MOS transistor.
Further, a mirror circuit section is provided. This mirror circuit section is having a) a fourth conductive MOS transistor whose source is connected to the power-supply potential and gate is connected to a gate of the third conductive MOS transistor, and b) a fifth conductive MOS transistor and a sixth conductive MOS transistor whose sources are connected to a drain of the fourth conductive MOS transistor.
Further, data input terminal, a negative output terminal, and a positive input terminal are provided.
Further, a data transmission switch circuit section is provided. This data transmission switch circuit section is having a) an inverter circuit which inverts data input through the input terminal, b) a seventh conductive MOS transistor whose gate is connected to an output terminal of the inverter circuit and a drain is connected to a drain of the fifth conductive MOS transistor, c) an eighth conductive MOS transistor whose gate is connected to the data input terminal and a drain is connected to a drain of the fifth conductive MOS transistor.
Gate of the fifth conductive MOS transistor being connected to the data input terminal, gate of the sixth conductive MOS transistor being connected to the output terminal of the inverter circuit, drain of the seventh conductive MOS transistor being connected to the negative output terminal, and drain of the eighth conductive MOS transistor being connected to the positive output terminal.
Further, an offset level adjusting circuit section is provided. This offset level adjusting circuit section is having a ninth conductive MOS transistor whose source is connected to GND and drain is connected to sources of the seventh and eighth conductive MOS transistors.
Further, a resistance bias voltage generating circuit section is provided. This resistance bias voltage generating circuit section is having a) a resistance whose one terminal is connected to GND, and b) a tenth conductive MOS transistor whose source is connected to the power-supply potential and gate and drain being connected to the other terminal of the resistance.
Further, the differential output circuit, which uses LVDS in order to obtain high-speed, low-voltage and low-noise transmission, is provided with the reference voltage circuit, which outputs a constant voltage even if temperature, power-supply voltage and semiconductor manufacturing process varies.
Further, a constant-current circuit section is provided. This constant-current circuit section is having a) a reference voltage circuit which outputs a constant voltage even if any of the temperature, power-supply voltage and semiconductor manufacturing process varies, b) a first conductive MOS transistor whose source is connected to GND, b) a second conductive MOS transistor whose drain is connected to a drain and gate of the first conductive MOS transistor, c) a first resistance whose one terminal is connected to a power-supply potential and the other terminal is connected to a source of the second conductive MOS transistor, d) an amplification circuit to a negative input terminal which the output terminal of the reference voltage circuit is connected, a positive input terminal is connected to a node between the source of the second conductive MOS transistor and the first resistance, and an output terminal is connected to a gate of the second conductive MOS transistor.
Further, a mirror circuit section is provided. This mirror circuit section is having a) a third conductive MOS transistor whose source is connected to GND and gate is connected to the gate of the first conductive MOS transistor and drain of the second conductive MOS transistor, and b) a fifth conductive MOS transistor and a sixth conductive MOS transistor whose sources are connected to a drain of the third conductive MOS transistor.
Further, data input terminal, a negative output terminal, and a positive input terminal are provided.
Further, a data transmission switch circuit section is provided. This data transmission switch circuit section is having a) an inverter circuit which inverts data input through the input terminal, b) a sixth conductive MOS transistor whose gate is connected to an output terminal of the inverter circuit and drain is connected to a drain of the fifth conductive MOS transistor, c) a seventh conductive MOS transistor whose gate is connected to the data input terminal and drain is connected to a drain of the sixth conductive MOS transistor.
Gate of the fifth conductive MOS transistor being connected to the data input terminal, gate of the fourth conductive MOS transistor being connected to the output terminal of the inverter circuit, the drain of the fourth conductive MOS transistor being connected to the negative output terminal, and the drain of the fifth conductive MOS transistor being connected to the positive output terminal.
Further, an offset level adjusting circuit section is provided. This an offset level adjusting circuit section is having a second resistance whose one terminal is connected to the power-supply potential and the other terminal is connected to sources of the third and fourth conductive MOS transistors.
Further, in the differential output circuit, a resistance bias voltage generating circuit section is provided. This resistance bias voltage generating circuit section is constituted so that the first and second resistances are replaced by eight and ninth conductive MOS transistors biased to a linear area, and gate voltages of the eight and ninth conductive MOS transistors are supplied, and a third resistance whose one terminal is connected to GND is serially connected to a tenth conductive MOS transistor whose a source is connected to a power-supply potential and a gate and a drain are connected to the other terminal of the third resistance.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.